Electronics and Electrical Power

SOFTWARE CATALOG
Electronics and Electrical Power
Electronics and Electrical Power
Solar Arrays, Batteries, Cabling, Grounding, Converters, Electrical Analysis
LEW-20090-1
CCSDS Optical Communications High Photon Efficiency Telemetry Signaling Transmit Waveform VHDL/Verilog
This technology is a VHDL and Verilog implementation of the Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency Telemetry Signaling waveform. The CCSDS 142.0-B-1 Blue Book from August 2019 is implemented. The implementation includes a data source, transfer frame synchronization marker attachment, slicer, randomizer, cyclic redundancy check, termination bit attachment, convolutional encoder, code interleaver, accumulator, pulse position modulation (PPM) symbol mapper, channel interleaver, codeword sync marker attachment, symbol repeater, slot mapper, and guard slot insertion.
U.S. and Foreign Release
ARC-17046-1
Physics-Model-Based Wiring Fault Detection Toolbox for MATLAB
Providing a toolbox of functionality for MATLAB, this NASA-developed software detects precursor wiring faults (e.g., chafing) in shielded impedance-controlled cabling using measurements from off-the-shelf, time-domain reflectometry or vector-network analyzer hardware. The technology combines high-fidelity analytical physics models for signal propagation with fast Bayesian inference algorithms for intrinsic cable and fault-parameter retrieval.
Open Source
LEW-19083-1
Space Telecommunications Radio System (STRS) Reference Implementation (RI)
The STRS Reference Implementation is a demonstration of the STRS architecture. The STRS Architecture Standard for software defined radios (SDRs) is an open architecture for NASA space and ground radios. The STRS standard provides a common, consistent framework to develop, qualify, operate and maintain complex reconfigurable and reprogrammable radio systems. The STRS Reference Implemenation allows verification of capabilities and provides lessons learned for the improvement of the STRS Architecture Standard 1.02.
U.S. Government Purpose Release
LEW-19389-1
FPGA Code Development for the iPAS STRS Radio
The innovation is FPGA VHDL code written as part of the iPAS STRS Radio development. The purpose of the FPGA design is the implementation of the signal processing functions of the STRS radio architecture in the IPAS RAICs platform. The FPGA design will consist of two parts the FPGA wrapper and the test waveform. The FPGA wrapper implements each platform interface: Ethernet communication to the embedded processor for commanding and data streaming Digital-to Analog Converter (DAC) and Analog-to-digital converter (ADC) interface to the RF board RF Board Control and Configuration FPGA Clocking The test waveform does not fully implement all the signal processing functionality for a radio, but it exercises and demonstrates each interface in the FPGA wrapper. A future user of the platform for an STRS radio, would use the FPGA wrapper and replace the test waveform with their own radio signal processing functions. The FPGA design receives and processes commands and provides command control and data to the test waveform. It also receives and transmits streaming data from/to the embedded processor. The test waveform demonstrates each FPGA wrapper interface. To test transmit-side streaming, it can perform bit error rate testing on transmit-side PRBS streaming data. It can also generate PRBS streaming data packets for a receive-side streaming data source. The test waveform generates sine waves for the in-phase (I) and quadrature (Q) inputs to the RF transceiver. A BPSK modulator is included to modulate PRBS data from with the PRBS generator or from transmit-side streaming data. Captured I and Q samples from the RF transceiver can be streamed to the embedded processor where it can be plotted (if a sine wave) or bit error rate checked (if PRBS data) to demonstrate proper functionality of the RF board and its interfaces.
U.S. Government Purpose Release
LEW-19723-1
STRS Modular and Portable QPSK Transceiver Waveform for Software-Defined Radios
A QPSK transceiver waveform has been developed and implemented on a commercially-available ground-based software defined radio platform. The waveform utilizes legacy NASA forward error correction codes and Consultative Committee for Space Data Systems (CCSDS) data framing standards. It's controlled via web interface, and allows the user to multiplex between test (pseudo-random) and network-sourced data. From a specification standpoint, the waveform supports the following functionalities in both transmit/receive directions: QPSK modulation, continuously tunable data-rates up-to 6.144Mbps for RX and 24.576Mbps for TX, convolutional coding/decoding (rate 1/2, constraint length of 7), CCSDS-compliant randomization (131.0-B-2) and Advanced Orbiting Systems (AOS) data framing (732.0-B-2). The product consists of two main components: (1) the digital logic (VHDL) implementation for the Field Programmable Gate Array (FPGA) that does the required signal processing functionalities and (2) the command-and-control software portion that leverages the open-source Core Flight Executive (cFE) software suite and provides a graphical user interface to the waveform.
U.S. Release Only
GSC-17526-1
Real-Time Executive for Multiprocessor Systems (RTEMS) RAD750 Board Support Package (BSP)
The innovation is a board support package that provides a port of the open source Real-Time Executive for Multiprocessor Systems (RTEMS) real-time operating system and a full set of hardware drivers for the BAE Systems Inc. RAD750 single board computer.
U.S. Government Purpose Release
MSC-27118-1
NASA Universal Asynchronous Receiver Transmitter (UART) Intellectual Property (IP) and VHDL Code
The NASA_UART_Example is an Aldec Active-HDL project that contains the Intellectual Property (IP) files for a NASA developed Universal Asynchronous Receiver Transmitter (UART) and supporting files to implement an example of using the UART IP. The source files are a combination of Active-HDL block diagrams, Active-HDL state machines, and VHDL code. The block diagram and state machines compile down to VHDL code. All the source and compiled VHDL files are provided.
U.S. Release Only
LEW-19882-1
CCSDS Optical Communications High Photon Efficiency Transmit Downlink Waveform Matlab Model
This technology is a Matlab model of the Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency downlink transmit waveform. The model implements the CCSDS 141.1-R-1-v10 Draft Red Book from April 25, 2018. This includes a data source, transfer frame synchronization marker attachment, slicer, randomizer, cyclic redundancy check, termination bit attachment, convolutional encoder, code interleaver, accumulator, pulse position modulation (PPM) symbol mapper, channel interleaver, codeword sync marker attachment, symbol repeater, slot mapper, and guard slot insertion. The model can be used to verify FPGA implementations of the CCSDS standard.
U.S. Government Purpose Release
GSC-16586-1
Packet to Electrical Ground Support Equipment (EGSE) Interface Converter, Version 4.0
Developed using platform-independent language, this interface converter packet allows already-existing EGSE equipment to be supported on Windows and UNIX operating systems. The software is set up and controlled using XML-formatted files that define interface connections and data content.
U.S. Government Purpose Release
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