FPGA Code Development for the iPAS STRS Radio(LEW-19389-1)

The innovation is FPGA VHDL code written as part of the iPAS STRS Radio development. The purpose of the FPGA design is the implementation of the signal processing functions of the STRS radio architecture in the IPAS RAICs platform. The FPGA design will consist of two parts the FPGA wrapper and the test waveform. The FPGA wrapper implements each platform interface: Ethernet communication to the embedded processor for commanding and data streamingDigital-to Analog Converter (DAC) and Analog-to-digital converter (ADC) interface to the RF boardRF Board Control and ConfigurationFPGA ClockingThe test waveform does not fully implement all the signal processing functionality for a radio, but it exercises and demonstrates each interface in the FPGA wrapper. A future user of the platform for an STRS radio, would use the FPGA wrapper and replace the test waveform with their own radio signal processing functions.The FPGA design receives and processes commands and provides command control and data to the test waveform. It also receives and transmits streaming data from/to the embedded processor. The test waveform demonstrates each FPGA wrapper interface. To test transmit-side streaming, it can perform bit error rate testing on transmit-side PRBS streaming data. It can also generate PRBS streaming data packets for a receive-side streaming data source. The test waveform generates sine waves for the in-phase (I) and quadrature (Q) inputs to the RF transceiver. A BPSK modulator is included to modulate PRBS data from with the PRBS generator or from transmit-side streaming data. Captured I and Q samples from the RF transceiver can be streamed to the embedded processor where it can be plotted (if a sine wave) or bit error rate checked (if PRBS data) to demonstrate proper functionality of the RF board and its interfaces.